This invention relates to floating point operations, and more particularly to a method for detecting leading-ones or leading-zeros for the results of floating point operations, using input operands rather than waiting until the results are available.
In floating-point processors, a leading-1 detection mechanism is required in effective subtract operations and in integer-to-floating-point conversion operations. The sequence of four pipeline operations needed to implement an effective subtract operation when the absolute exponent difference is less than or equal to one, in a typical processor, are:
1 Align smaller operand and subtract (done in adder) PA1 2. Complement fraction if sign is negative, and detect leading-1 position (done in leading-1 detector circuit) PA1 3. Normalize the fraction (shifter) PA1 4. Round the result if needed (done in adder) PA1 1. Align smaller operand and subtract; Detect leading-1 or leading-0 position in the input operands (done in adder and leading-1 detector circuit) PA1 2. Normalize the fraction (shifter) PA1 3. Round the result if positive, or negate the result if negative (done in adder)
The second pipeline stage can be merged with the first, eliminating one pipeline stage and thus speeding up the process, if the leading-1 detection is done on the input operands instead of on the result. The sequence of three pipeline operations for an effective subtract with exponent difference equal to zero or one, with leading-1 detection at the inputs:
Leading-0 detection is required in the case where the result may be negative, such as an effective subtraction with an exponent difference equal to zero. Rounding is not needed for this particular case.
One example of a prior circuit for determining the leading-one/zero directly from the adder inputs is disclosed by Kershaw et al in "A Programmable Digital Signal Processor with 32b Floating Point Arithmetic," ISSCC 85, pp. 92-93, February 1985.
Another example of a method of is disclosed by Hokenek et al in "Leading-zero anticipator (LZA) in the EBM RISC System/6000 floating-point execution unit," ]IBM J. Res. Develop., January 1990, pp. 71-77. This circuit carries out processing of leading ones and zeros in parallel with floating-point addition.